Too many spinning plates

Sorry I have neglected this blog for over a year. I’ve come to realise I have too many ideas on the go at once, which whilst great for variety, does not allow much progression. I took a long hard look at what I was doing and I have suspended all work on project Hermes (CD32 expansion) indefinitely. It was not due to technical issues, it was due to support. The original intent of the project was to produce 100 assembled and tested PCBs and then via a third party, sell them, I had a tacit agreement on this. The realisation, in part driven by bad experience in the day job, was that a more complicated design than a ‘simple’ ATX or floppy adaptor, would take a significant amount of my time to support. Currently I spend 8-10 hours a month dealing with enquiries, order packing and support requests for the products I currently sell. Allowing for a design that is more 4-5x more complex with more variables, I can easily see that the support time will increase considerably, easily to 10x the current level. When (not if) it gets to that level of effort, it becomes more of a chore than a fun hobby. This is the time to stop.

I will continue to support the products I currently sell. There are two small, Amiga related, projects, in the final stages of development. Will release details when they are ready. Once released and manufactured, they will be the last Amiga specific projects I work on.

The other projects I work on are increasingly micro-controller based and two of them use CPLDs for video and logic functions. These projects are more generic retro projects. I also develop designs for Radio Control systems, more on this when I finish them. Like most of my current projects, all the design data will be publicly available.

I realise this announcement will disappoint some people. Over the past 10 years, I have, on average, finished 7 projects a year. The past year, I’ve done 2. I’m older now and life has other distractions so I’ve decided to do what is best for me and to actually achieve success on smaller, more manageable projects rather than failure on one large project.

Thank you,

Ian

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Synchronise your video engines

The importance of applying the correct video sync signal to your TV, monitor, scan converter, HDMI adaptor or projector.
This post tries to answer some of the many questions I get relating to the GBS-8200 and non-standard video types. I will
provide information on how to help identify the correct synchronisation or sync signal for shortness, for common applications
and describe some of the effects you may see when you get it wrong. I do not have a guaranteed fix for any problem, this is more
a how to guide to help you fix any issues you may encounter.

Topics covered in this post

What are synchronisation(sync) signal(s)?
Understanding your composite from your H/V and Sync On green type?
Basic information on video sync timings, PAL, NTSC, CGA, EGA, VGA.
Converting video sync amplitude
Sync strippers/cleaners/separators
Best options for the GBS-8200

What are synchronisation(sync) signal(s)?

Let’s start with a basic description of a sync signal. I took the following from the Tektronix Video Measurements glossary:

Sync – a) Abbreviation for synchronization. Usually refers to the synchro-
nization pulses necessary to coordinate the operation of several intercon-
nected video components. When the components are properly synchro-
nized, they are said to be “in sync”. b) Signals which control the sweep of
the electron beam across the face of the display. The horizontal sync, or
HSYNC for short, tells the display where to put the picture in the left-to-
right dimension, while the vertical sync (VSYNC) tells the display where
to put the picture from top-to-bottom. c) The portion of an encoded video
signal which occurs during blanking and is used to synchronize the opera-
tion of cameras, monitors, and other equipment. Horizontal sync occurs
within the blanking period in each horizontal scanning line, and vertical
sync occurs within the vertical blanking period.

With the move to LCD displays we are not concerned with movement of an electron beam but it is useful to understand how
the horizontal and vertical sync signals play their part in creating the display you see.

Basic information on video sync timings, PAL, NTSC, CGA, EGA, VGA.

 

Video type Horizontal
frequency
Vertical
frequency
Interlaced? Number
of lines
Notes
 PAL  50 Hz  15.625 KHz  Yes  576 active  (1)
 NTSC  59.94 Hz  15.750 KHz  Yes  480 active  (1)
 CGA  60 Hz  15.750 KHz  Yes  200  TTL signals. (2)
 EGA  60 Hz  15.750 KHz/21.80 KHz  No  350?  Vertical frequency changes depending on the mode,
200 line display is 15.750KHz, 350 line display is 21.80 KHz. TTL signals
 VGA  60 Hz  31.469 KHz  No  480+  Lowest resolution shown, extends up to 2014×1536

(1) Quite often when a system states PAL or NTSC output, e.g. a camera, the signal is a composite video signal. For higher quality
conversions, either a Y/C(S-video) or an RGB output is preferred. The sync is embedded with the video.
(2) CGA is unique in that it uses TTL digital signals, with an intensity pin to get 16 colours. If you don’t have an adaptor board to convert
the RGB+intensity to analogue, most converters will struggle. Has separate H/V syncs

You will note that I state that NTSC has a vertical frequency of 59.94 Hz, where as most of the other standards are 60Hz, indeed some
literature states 60 Hz for NTSC. In practice, most of the time this 0.06Hz deviation makes no difference.

Understanding your composite from your H/V and Sync On green type?

So you have a retro game console or computer and you want to connect it to a modern LCD  display or a projector, should be straightforward right?

Depending on the equipment you may have a single signal or multiple types. The table below details the main types:

Sync type Voltage Description
Composite video 1V Normally a yellow plug, contains video and a combined sync. Used by SCART inputs.
CSYNC TTL (2-5V signal) Output by some graphics cards or a TTL signal from retro equipment. It only contains timing information, no video.
HSYNC TTL (2-5V) signal Provides the horizontal video timing, which details the start and end of a line.
VSYNC TTL (2-5V) signal Provides the vertical sync timing, which describes the frame rate.
Sync-on-green 1V A -0.3V sync signal attached to a 0.7V peak green video signal.

An important point is that you need to know what signal amplitude is expected by your TV/monitor/scaler/converter. A common mistake, is to connect
a CSYNC signal, either from a retro device or a computer, to a SCART socket. The SCART standard expects composite video on pin 20, if you feed in a
TTL CSYNC signal, you could be supplying a signal upto 5x higher than expected. My Amiga SCART  and Atari SCART cables fixed multiple video issues,
with a simple fix to the sync amplitude, by adding a series resistor on the sync signal.

I show a TTL signal as a 2-5V signal, for good reason. A retro computer or video system will have 5V logic, a logic 1 output can be from 2.4V (min) to 5.5V(max).
When you connect one of these signals to a 3.3V video chip, like that on the GBS-8200, you are damaging the device as the input signal exceeds the supply voltage.
The ESD protection diodes conduct and soft of allow the system to work, but they are not meant to be used continuously and will fail, at the same time as your board.
The next section details various methods of converting sync signals.

Converting video sync amplitude

So how do you convert a composite video to separate h/v sync or reduce a 5V TTL signal to 3.3V LVTTL or any or a number of options?

Some conversions are simple and can use readily available modules, others need a little circuit board. The table below will help:

From To Solution
Composite  CSYNC (3.3V or 5V)  Sync stripper
 Composite  H & V Sync (3.3V or 5V)  Sync stripper2
 CSYNC  Composite (1V) level  Resistor circuit
 H & V Sync  CSYNC (3.3V or 5V)  OR/XOR gate
 Sync on green  CSYNC (3.3V or 5V)  Sync stripper2
 Sync on green  H & V Sync ((3.3V or 5V)  Sync stripper2
 5V TTL  3.3V TTL  Level converter

Examples of each circuit element are shown in the sections below. What is not shown are power supplies and connectors. This is left to the developer,
though for all circuits shown, a simple linear regulator would suffice.

Sync strippers/cleaners/separators

When I first started researching video adaptors and converters I came across ‘sync strippers’ and wondered what they were. They are relatively simple
circuits, based around commonly available  sync separators, the most widely used being the National Semiconductor (now Texas Instruments) LM1881.
They accept a composite video signal and strip the colour burst off the signal and in the case of the LM1881, output a 5V TTL CSYNC signal.

Syncstripper circuit

LM1881-circuit

Taken from the LM1881 datasheet. Widely used as it’s a readily available part in a DIP package.
There are two limitations of this part:
1) The 5V TTL output is not compatible with modern TVs/HDMI adapters/projectors. It needs a level translator.
2) It does not provide a separate horizontal sync output. If your adaptor only needs CSYNC, great, otherwise try the Syncstripper2 circuit below.
You may get away with using CSYNC for HSYNC but it is by no means guaranteed.

Syncstripper2 circuit

LMH1980-circuit

Again taken from the datasheet. Being a surface mount device will put some people off, the VSSOP-10 package is a bit small but you can
easily buy a SSOP to DIP adaptor off ebay. If you power it from a 3.3V supply, the logic level outputs will be compatible with modern
display devices, no external converter needed. It provides true H/V and C sync outputs and works with a wider range of video types and frequencies.

Would an adaptor board with this circuit, video amplifier and maybe a scanline generator be of interest?

Potential divider and logic level converters

Resistive potential divider circuits
The first circuit converts 5V TTL signals to 1V CSYNC for SCART

5VTTL-SCART

This is a simple potential divider circuit. The output voltage is 75/(75+330) x Vin which gives an output voltage that is ~18% of the
input or around 0.92V.

The second variant is for the GBS-8200 or a modern monitor that is not 5V tolerant.

5VTTL-LVTTL_resistors

With a VESA VGA video monitor or equivalent, the input impedance of the display is much higher, in this instance, 2K. As the aim is to
reduce the signal to be approximately 3.3V, we reduce the amplitude by 27-30%.

One disadvantage of this circuit is that the RC time delay does affect the rising/falling edge of the sync pulse slightly. In most circumstances,
this will not matter but some systems may have issues if the time delay extends past a 100ns rise/fall time. For a cleaner, faster signal, use
logic devices.

Transistor logic level convertor

An improvement is to use a transistor circuit.
FET_level_Translator

This circuit is simple to implement and provides faster edges than resistor networks. You will also find this on ebay as a
level translator for the Arduino, it is acceptable to use it for video.
LevelConverter-L

 

OR/XOR sync combiner circuit
HV_Sync_Csync

The circuit shown above has the option to use either an OR gate or an XOR gate to combine separate HSYNC and VSYNC into a CSYNC signal.
Most of the time, the OR gate will suffice. Depending on the display you interface, you may need to invert the vertical syn portion,
hence the option to use an XOR gate. The 33R resistors were added to damp any ringing when driving long cables. With careful selection of the logic
family, you can use a 5V tolerant part, operating from a 3.3V supply.

Effect of supplying a 5V signal to a 3.3V device

This could be very detailed and lengthy discussion detail the effects of electromigration and it’s detrimental impact on device reliability. I’ll summarise,
DON’T CONNECT 5V LOGIC TO MODERN MONITORS OR ADAPTORS!
Whilst it will appear to work, you may see odd effects, occasional display artefacts or issues displaying a stable image occasionally. If a device is powered
from 3.3V and you feed in 5V, you are exceeding the power supply by upto 1.7V, not a good start. The internal ESD protection diodes, will clamp the signal
to around 3.9/4.0V, which you might think is OK. The clamping action distorts the signal and can cause the video display/adaptor to incorrectly sample the sync signal.
The ESD diodes are only meant to  have short term use to protect from static electricity, which is normally a short, sharp shock. If they are continuously used, they
will fail and when they do, the full 5V signal is fed into the IC. Depending on many factors, the distortion will get worse but one thing is 100% certain, the device will fail.

Best options for the GBS-8200

I would recommend as a minimum that any sync signals are scaled using at least a potential divider circuit or a transistor level shifter as they are readily
available, providing your source produces a C sync signal. If you need to to combine H and V Sync, use the logic circuit shown above.
If your system provides a composite video signal, use one of the sync strippers but ensure you condition the output to be 3.3V LVTTL compatible.

Summary

I hope this guide has been useful and informative. It is only meant to provide guidance on common issue I have encountered when inter-connecting various video
systems it is not a definitive guide of what you must do. Sometimes you need to experiment, if you have an oscilloscope, make some measurements.

I’ll be taking a break for a bit whilst I get busy with the CAD tools but I will read and respond to your comments.

May the 4th be with you

Forgive me it has been six months since my last posting, I have been a little busy.

Project Hermes is still in development but has progressed nicely. I started my review work on the design back in March 2016 and made a few tweaks to the design. The review schematics are  here: Hermes_development. One of the principal design requirements was to make it work within the CD32 power/space/performance envelope. One are the design was struggling with a little was power. Most of the anticipated power consumption was in the 5V to 3.3V converters for all the new logic and 2xCPLDs. One evening, with some help from Ti’s WEBBENCH(R), I had a solution that nearly halved the power consumption of the card. The BOM and schematics were updated accordingly.

When you look at the circuit on page 3 (which is not sexy), you may wonder why that was a few hours work. Component selection, simulations, schematic and BOM updates take time but the task is now done. This is one of many little tasks to complete.

The biggest challenge has and still is the programmable logic. I have a preliminary design which needs a test bench to prove it. I have ‘re-used’ some concepts from other projects but very little code. A few designs I looked at for the 6800/68020 processor bus used asynchronous logic. Whilst this will work, it does have the potential to cause a metastability problem. As someone who works with high integrity hardware, the design needed to be changed to a synchronous system. To speed up the logic decode, a 28 MHz clock is generated from the 14 MHz clock provided by the CD32. This ensures I have a higher speed, time aligned, clock for the logic decode and to help reduce the need for wait states. It does not convert the design into an accelerator!

It was whilst developing the programmable logic that a clash of projects occurred, something which took time to effectively resolve.

One of the features added by the MIA CPLD was the floppy disc interface. The core design was based on the CD32 floppy design on Aminet. One of my other projects was a prototype floppy interface in VHDL for the classic Amiga. It made sense to finalise that design before incorporating that design into Hermes. The basic double density only design has been incorporated after the final compliance testing was integrated with my A1200. In the near future I plan to release the V3 floppy interface, with the highly experimental, HD support. If I can get the HD support working reliably, it can be incorporated into Hermes.

The second conflict was from my Retro Video Adaptor, another project, which looking at that page, has gone nowhere since 2013. It’s not the whole truth it stalled for good reason, it would not work reliably with 240p/288p video. The basic concept was fatally flawed. It was inspired great success achieved using these video decoder parts with non-standard video but the tricks I learnt did not work with the Amiga! Without using timebase correction on the video output, I could not get YPbPr or HDMI outputs to work reliably. It was from this issue that I initially started playing with the GBS-8200 as this has a timebase correction feature. The critical feature of the GBS-8200 is that it has a framebuffer memory to convert the 240p(NTSC) and 288p(PAL) video to a higher resolution and provide a 60Hz output at a standard resolution. Without a stable output conversion, the downstream video output can not be converted to YPbPr or HDMI. It is this issue with 240p/288p video that causes many SCART to HDMI adaptors to fail as they do not know how to handle this video system. Some will interpret 240p as 480i (NTSC) and de-interlace, thus causing fuzziness. The same goes for 288p being interpreted as PAL video. Switching off the de-interlacer greatly improves the GBS-8200 video output with 240p/288p.

Tecnobabble out of the way, how is this relevant to the long delays on Hermes?
I have been looking into incorporating an HDMI output into the design. Handling the audio is easy, I have a stereo audio ADC for that that outputs the correct transport stream, it’s just the Amiga video I need to solve. Some experiments with a small FPGA to ‘adjust’ the timing were trialled with no success. Experimenting with the GBS-8200, I have seen what a system that can re-time and re-scale the video can achieve, whilst being fully aware of the issues of motion compensation and blurring among other artefacts. It was with regret that the implementation of an HDMI interface will not be part of the Hermes design. This decision was made due to the amount of time required to implement a reliable interface. It will be better to run the two projects in parallel and maybe add this in at a later date if a solution becomes viable. I have a candidate solution which is undergoing technical evaluation.

Someone will ask why don’t I use the Vampire FPGA accelerator and HDMI core?
The HDMI output is incorporated into the CPU core design and associated FPGA. The Vampire design is a very clever implementation but currently only supports 68000 instructions, the CD32 has a 68EC020 which supports a slightly different instruction set. The other reason is that at my current development rate, adding a new FPGA accelerator the design would never be finished!!! :p

The third and final conflict was finishing the updated Amiga/Atari floppy adaptor. I’ve just sent out the purchase order for a production run of 75 units. Yes you did read that correctly, the new design has been updated to work with the Atari ST/TT/Falcon in double density mode. This was a late design addition that delayed production by 2 months whilst a new prototype was successfully built and tested.

What’s next?

I still have a few changes from my design review to incorporate, mainly to improve testability and reduce emissions. Once complete, I’ll finish tracking the PCB. The prototype PCB will be a six layer PCB, this will make it easier to track and to provide some controlled impedance signals. Experience gained from getting the existing adaptor PCBs has helped me find lower cost quality PCB suppliers and assemblers.

I’ll answer another question, why have I not just made a prototype of the design I had 6-9 months ago?

Cost. A batch of 3 assembled prototype PCBs would cost >£500. It would be a bit cheaper if I assemble the prototypes myself. I’d rather spend a bit longer doing my innate design checks/double checks before committing to a prototype.

I will try and update this blog more often. There’ll be another post shortly related to the GBS-8200 experiments.

May the force be with you!

Being creative on cyber monday

It has been some time since my last post, I meant to post earlier but got a bit distracted reviewing and deleting 24 emails and text messages I had regarding Black Friday! Cyber Monday added another 16 emails. Decided to be creative and write another blog post instead.

First of all, after a few unforeseen delays, the ATX power adaptors will be available soon. My expected delivery date from the manufacturer is 25/12/2015, a nice early christmas present! It will take a few days to get the boards programmed and tested once complete I will list the adaptors for sale on my website. Realistically, it will be January 2016.
The CDTV ATX adaptors are in stock, as are the audio mixer PCBs.
The smaller floppy adaptors (for double density Amiga use) will follow in approximately 2 weeks, so middle of January. A late change for further use, has delayed sending this order out to manufacture.
Pricing is largely unchanged:
CDTV power adaptor £9
picoPSU adaptor £10
Mega adaptor (replaces original and big box) £11
Audio mixer PCB £4
Postage and packaging to be added to all orders.

Getting PCBs fabricated is easy, I have used multiple vendors with comparative ease. Getting PCBs fabricated and assembled, for a reasonable price is another story. I contacted 7 companies for quotes and only got responses from 2 of them. I guess small quantities (75 of each PCB) was too low for some of them. The company I chose to manufacture and assemble the PCBs has been good, so far. With a few minor changes and advice from them I managed to remove one of the higher costs from the Mega adaptor PCB by removing the need for 2Oz copper to take the power, this halved the PCB costs. Hopefully I will not be disappointed with the assembled units when they arrive at Christmas.

I do try and respond to comments on the blog as soon as possible. I added the information regarding my upcoming projects to try and reduce the number of ‘is it done yet’ emails I’m getting. This blog and my development projects are a hobby activity, I have a full time job working in the electronics industry, so sometimes it is necessary to take a break from electronics! Sometimes work is not fun but at least I get paid to do it, if the ‘hobby’ ceases to be fun, it’s time to stop and do something else. I am committed to my current projects, just taking my time to get them right 😉

Project Hermes is one of my more popular projects, the current quick status is this:
Schematics complete and in internal review.
Changes made to fix potential EMC and signal integrity issues.
First draft PCB layout in progress.
Feeding in some lessons learned to reduce the PCB costs

ETA 2016. See my comments in the previous paragraphs.

The other project I have many comments about is regarding my experiments with the GBS82XX video cards and retro games hardware. I started developing an Arduino programme/sketch that reads the numerous status registers, decodes the input video type and then sets the correct output display. I had a bit of fun with 3.3V/5V I2C interfaces, fixed with a cheap level converter from Squirrel Labs. It needs a lot of work to finish the basic input testing and resolve a few bugs and is not currently in a format to release. I know what I need to do and roughly how to do it, but I can’t release anything yet as it will leave more questions than answers. This will be a nice project to experiment with over the Christmas break!

I’m not going to respond to any further questions of ‘can you make this work with system X’ or ‘why does this not work with my antique video system Y’. Sorry to be so blunt but I have other things to do. I am working on my retro video guide, which when finished (and published on my website), will help you to resolve the more common issues and hopefully give a better understanding of the vagaries of video.

That’s all for now, I plan another update by year end, hopefully with some pictures.

So what’s taking so long?

I’m sure the followers of this blog have been asking the same question.

Due to other pressures/commitments I stopped all development work for the first 5 months of 2015 and have recently resumed. There is a backlog of work and projects to finish, which is progressing.

The existing Amiga adaptors I sold have been updated, new, simpler,  ATX power adaptors are in prototype PCBs, once testing is complete, a production order will be placed. Likewise the floppy drive adaptor has been updated, the new PCB is much smaller and easy to manufacture. Have also updated the un-released V3 design to support USB/SD card floppy adaptors internally/externally and experimental HD support.

Previously the Amiga adaptors were hand made by myself. This was getting time consuming as the volume of orders was increasing, great for business but I was struggling to make enough in batches to deliver. To alleviate this, all new designs will be outsourced to UK based contract manufacturers. This leaves me more time to design and test products.

Project Hermes is progressing, I have the core of the MIA CPLD coded but not tested. The schematic took longer, due to my decision to use Designspark, which was a big mistake. After getting rather frustrated with the tool, I ditched it and went back to the familiar Eagle CAD software, which I can use. I’ve been using Mentor Graphics tools for 19 years, Eagle for 12 years and used OrCAD for a bit, Designspark was the worst I’ve used!

I’ve written the Arduino code for the GBS-8200 board to detect the incoming video and scale/de-interlace accordingly but have not tested it yet. It’s a lower priority project at the moment but one I want to return to in the future.

In my next update, I’ll show the assembled prototype PCBs of the Amiga adaptors and the complete schematics for project Hermes. Hopefully June/July time.

Regards,

Ian

Working away, making some progress

Hi,

Sorry for the lack of updates recently, life, the universe and everything else has interfered.

I want to discuss the following topics in this post:

Progress
Pre-orders
Extra features (avoiding feature creep)

Progress on Project Hermes

It’s continuing at a reasonable pace. I am behind schedule but I have defined a list of 15 critical tasks that need to be completed before a prototype PCB can be sent for manufacture. I have currently ticked off 3 items.

A diversion, now a planned task, was the IDE interface. The original idea was to utilise the IDE68K design as-is. This has not proven to be the case. When drawing out the schematic I noticed that a few 68EC020 signals were missing. After re-reading the manual, I noticed a few differences. The MC68000 and MC68EC020 output some signals at different clock phases. So the existing design would need some tweaks. Alexh over at EAB converted the ABEL code to VHDL (my preferred HDL). When I compiled it, targeted at the XC9572, as used originally, it did not fit, it needed 74 macrocells from a 72 macrocell part. As no parts had been ordered at this stage, it was easily swapped to a 144 macrocell XC95144 device, as used for the MIA CPLD.

To verify the IDE interface and eventually the Memory Interface Adaptor (MIA) design, I need a 68020 testbench to stimulate both designs. The last time I wrote a VHDL test bench was back in the advanced VHDL training class, back in January 2012, so I’m a little rusty. One of my personal development aims for this project was to improve my VHDL/CPLD skills.

So what I thought would be an easy tasks, grew in size. I must be confident that the IDE interface and the MIA CPLD will work before committing to hardware. Reading some of the user feedback on the IDE68K design reinforces this decision.

I typically have a few hours a week for my design projects, the little details can easily take the available time but I would rather find them now when it is easier and cheaper to fix them.

Not sure If it has been made clear but the design is intended to fit inside the CD32, similar to the venerable DCE SX32. Indeed, the PCB footprint will be no larger than this, though I expect a smaller PCB.

Pre-orders

Pre-orders are not required.

I would not start a project if I could not fund it and I will not accept funding for pre-orders. The current development phase will have 3 prototype cards, that has been funded from the profits made from the current range of Amiga adaptor PCBs I sell. Ordering of critical components has commenced, the first batch arrived today and other components will be ordered shortly.

Extra features (avoiding design creep)

If it seems like I am being very harsh shooting down extra design features, I have good reason, feature creep can kill a project. It will take some time to finish the first 3 prototypes. I have added some expansion connectors to allow me to trial other ideas later but without a prototype PCB, other features are a moot point.

Some features, like making the IDE/compact flash slot accessible from the side of the CD32 are accommodatable adding network interfaces or even an SD card interface add cost and complexity.

Once I have some working prototypes, I can experiment, then other features may get added.

Cost is a big issue for the design. Of the expected £120 retail cost, around £50 of that cost is in the manufacturing of the PCB and assembly of the module.  Work is ongoing to lower the module costs.

The most expensive components are:
XC95144 CPLD, SRAM, Compact flash connector and the 5V/3.3V logic. I looked at adding a Real Time Clock, with parallel interface, it would have cost more than the CPLDs!

That’s all for now

Well it worked in the simulations!?

Time for a slight change of topic, leaving project Hermes for a while and detailing some of the fun of developing ‘simpler’ circuits.

I have just finished a long over-due update of a simple, single supply audio mixer, primarily aimed at the Amiga, details are here: http://www.ianstedman.co.uk/Amiga/designs/Audio_Mixer_MK2/audio_mixer_mk2.html, this is a simple design, based on a classic summing amplifier. For the original prototype, designed back in 2012, I simulated the circuit using a SPICE simulator, all worked well, tracked the PCB, ordered a PCB and built it. It did not work!

The output of the op-amps was a DC level, it would not respond to any input stimulus. I isolated the other input, in case this was causing an offset, no joy, isolated the inverting output stage, no joy. Left the workshop tired and confused before I did something crazy.

The design uses an LM358 operational amplifier, nothing special, it’s a voltage feedback device that can run off a single supply. It was the single supply that was part of the problem. I created a 1/2Vcc reference, buffered by another LM358, for the other devices to use, this worked.

A search of the Texas Instruments website, found an application note, AN-116, http://www.ti.com/lit/an/snoa662b/snoa662b.pdf, in there was a critical note, missing from the datasheet,

The LM358 will operate satisfactorily in balanced supply operation so long as a load is maintained from output to the negative supply

, this is achieved by adding a 10K resistor from the output to the negative supply, which is GND for a single supply. Ironically, if you use a non-inverting amplifier, the Vq resistor is not required, but to have a summing amplifier (to mix audio signals) requires an inverting amplifier.

So based on simulations which worked well, I spent £40 getting two PCBs fabricated, which did not work! An expensive lesson learnt. It also show the importance of a prototype to prove the theory.

It took about two years to go from the prototype to a final PCB, which is now available to purchase (marketing plug), http://www.ianstedman.co.uk/Sales/sales.html.

The final design works well, even if I do say so myself. The frequency response has improved slightly, it covers the full 20Hz to 20KHz range, more than I can hear, it cures the harshness of the left/right Amiga audio output and looks quite nice.

There is one final tweak to the design, which involves a few component changes. The ‘Better Paula’ circuit implementation, is slightly wrong. It requires a different mix ratio, which thankfully is just a few resistor changes. I will test this shortly and update the MP3 samples on my website.

This audio mixer was a simple design, which all told, with design, re-design (grr), PCB tracking, component selection and website updates to document it all has taken around 30 hours to develop. Surprising but not un-expected.

That’s all for now. Back to digital electronics.